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Atmel /ATSAM3X8C /UOTGHS /DEVEPTISR[2]

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Interpret as DEVEPTISR[2]

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TXINI)TXINI 0 (RXOUTI)RXOUTI 0 (RXSTPI)RXSTPI 0 (NAKOUTI)NAKOUTI 0 (NAKINI)NAKINI 0 (OVERFI)OVERFI 0 (STALLEDI)STALLEDI 0 (SHORTPACKET)SHORTPACKET 0 (DATA0)DTSEQ 0 (0_BUSY)NBUSYBK 0 (BANK0)CURRBK 0 (RWALL)RWALL 0 (CTRLDIR)CTRLDIR 0 (CFGOK)CFGOK 0BYCT

DTSEQ=DATA0, CURRBK=BANK0, NBUSYBK=0_BUSY

Description

Device Endpoint Status Register (n = 0)

Fields

TXINI

Transmitted IN Data Interrupt
RXOUTI

Received OUT Data Interrupt
RXSTPI

Received SETUP Interrupt
NAKOUTI

NAKed OUT Interrupt
NAKINI

NAKed IN Interrupt
OVERFI

Overflow Interrupt
STALLEDI

STALLed Interrupt
SHORTPACKET

Short Packet Interrupt
DTSEQ

Data Toggle Sequence

0 (DATA0): Data0 toggle sequence

1 (DATA1): Data1 toggle sequence

2 (DATA2): Reserved for high-bandwidth isochronous endpoint

3 (MDATA): Reserved for high-bandwidth isochronous endpoint
NBUSYBK

Number of Busy Banks

0 (0_BUSY): 0 busy bank (all banks free)

1 (1_BUSY): 1 busy bank

2 (2_BUSY): 2 busy banks

3 (3_BUSY): 3 busy banks
CURRBK

Current Bank

0 (BANK0): Current bank is bank0

1 (BANK1): Current bank is bank1

2 (BANK2): Current bank is bank2
RWALL

Read-write Allowed
CTRLDIR

Control Direction
CFGOK

Configuration OK Status
BYCT

Byte Count

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data